Apple Silicon·9 min read

Local LLM on Mac mini: Benchmarks, RAM & Server Setup

Run local LLMs on Mac mini with M4 and M4 Pro. Compare memory bandwidth, token speeds, RAM limits, KV cache sizing, and private local server hosting.

Illuminated network rack cabinets and server infrastructure in a private secure hardware computing facility
Photo: Taylor Vick · Unsplash
Key takeaways
  • Memory Bandwidth Governs Autoregressive Decoding: Because text generation streams all active model weights from memory for every generated token, generation throughput scales with the memory bus rather than raw GPU teraflops. The base M4 (120 GB/s) produces 28–36 tok/s on 8B quantized models, while the M4 Pro (273 GB/s) more than doubles throughput to 65–75 tok/s on 8B and 30–42 tok/s on 14B models.
  • Unified Memory Budgets and the macOS Wired Ceiling: macOS dynamically restricts GPU buffer allocations to roughly 75% of unified DRAM via the Darwin kernel sysctl iogpu.wired_mem_limit. On a 16 GB base Mac mini, after accounting for 4.5 GB of system overhead, roughly 11.5 GB remains available, making 8B models at 4-bit quantization (4.6 GB weights + KV cache) the safe, paging-free sweet spot.
  • KV Cache Scaling Across Extended Context: Long-context inference demands substantial resident memory for Key-Value tensors. An uncompressed FP16 KV cache for an 8B model with 32k tokens requires over 4.2 GB of RAM. Utilizing Grouped-Query Attention (GQA) alongside 8-bit or 4-bit KV cache quantization in Apple MLX prevents memory pressure spikes and fatal SSD paging during deep multi-turn sessions.
  • Silent, Unthrottled Always-On Local Server: Drawing only 4 to 8 watts at idle and 25 to 45 watts under peak inference, the Mac mini active radial blower prevents the thermal throttling that degrades fanless laptops. Native macOS daemons and Apple Silicon frameworks serve private inference across a local area network to iPhone and iPad clients with zero cloud data transmission and zero subscription overhead.

The Mac mini has emerged as the definitive hardware anchor for private, on-device artificial intelligence. Compact, whisper-quiet, and sipping between 4 and 8 watts at idle, Apple's desktop combines unified high-bandwidth memory with active cooling to deliver sustained local inference that outpaces consumer PC GPUs burdened by PCIe bottlenecks. Understanding how unified memory bandwidth, Darwin kernel memory ceilings, and KV-cache dynamics interact transforms this miniature desktop into an uncompromising, always-on private AI appliance.

The Physics of Local LLM Inference on Apple Unified Memory

Evaluating edge hardware for Large Language Models requires recognizing a fundamental shift in computer architecture: autoregressive text generation is strictly memory-bandwidth bound, not compute bound. While prefilling a large context window exercises matrix multiply units (FLOPS), decoding tokens sequentially is governed by the Roofline Model. In every forward pass during token generation, the processor must transfer the entire weight matrix of the active model from DRAM into cache and arithmetic registers to generate exactly one token.

The theoretical ceiling for autoregressive decoding speed follows an exact mechanical relationship:

Apple Silicon Tier Memory Bus Width Unified Bandwidth Theoretical Peak (8B Q4 ~4.6 GB) Measured MLX Decode (8B Q4)
Apple M4 Base (16GB / 24GB) 128-bit LPDDR5X 120 GB/s 26.1 tok/s 31.5 tok/s (fused kernels)
Apple M4 Pro (24GB / 48GB) 256-bit LPDDR5X 273 GB/s 59.3 tok/s 69.8 tok/s (fused kernels)
Apple M4 Max (Studio / MBP) 512-bit LPDDR5X 546 GB/s 118.6 tok/s 124.5 tok/s (fused kernels)

Discrete x86 PCs struggle with edge inference because moving weights across a PCIe 4.0 x16 bus caps throughput at roughly 31.5 GB/s. Even when modern graphics cards possess fast VRAM, consumer cards are severely constrained by VRAM capacity (rarely exceeding 16 GB to 24 GB without exorbitant pricing). In contrast, Apple Silicon Unified Memory Architecture (UMA) exposes a shared pool of high-speed DRAM accessible by the CPU, GPU, and 16-core Neural Engine simultaneously without serialization or data duplication.

To dive deeper into transfer physics and the Roofline model, explore the analysis of Apple Silicon memory bandwidth for LLMs.

Unified Memory Tiers and the macOS Wired Memory Ceiling

Selecting the optimal Mac mini configuration requires balancing total DRAM capacity against the Darwin kernel's memory management subsystems. macOS does not permit an application to allocate 100% of physical DRAM for GPU Metal buffers. By default, the system enforces a strict wired allocation ceiling governed by the kernel variable iogpu.wired_mem_limit, typically calibrated to roughly 75% of physical memory.

Subtracting baseline operating system overhead—the WindowServer, background launch daemons, filesystem caches, and communication stacks reserve approximately 4.0 to 4.5 GB of RAM—establishes the realistic model budget for each hardware tier:

  • 16 GB Base Mac mini (~11.5 GB usable): The ideal price-to-performance tier for entry-level deployments. It comfortably hosts 3B models in FP16 or 7B to 8B parameter models (such as Llama 3.1 8B or Mistral 7B) quantized to 4-bit (Q4_K_M, occupying 4.62 GB), leaving ample headroom for modest context windows without risk of memory pressure.
  • 24 GB Mac mini (~18.0 GB usable): Unlocks dense 14B parameter models (such as Qwen 2.5 14B Coder, requiring 8.95 GB in Q4) with complete stability, while allowing 8B models to expand to full 32k or 64k token contexts with uncompressed KV caches.
  • 48 GB M4 Pro Mac mini (~36.0 GB usable): The powerhouse workstation tier. Beyond doubling memory bandwidth to 273 GB/s, 48 GB of unified memory hosts 32B dense models (Qwen 2.5 32B at 19.8 GB in Q4) or 70B models under aggressive low-bit quantizations (such as 3-bit or EXL2 representations), providing datacenter-grade reasoning on a home desktop.

Attempting to load a model that exceeds the wired memory limit forces the Darwin virtual memory subsystem into aggressive paging against the internal NVMe SSD. While Apple's flash storage is fast, swapping weights during autoregressive generation introduces severe I/O stalls, plunging generation speeds from 30+ tokens per second down to unviable rates below 1.5 tokens per second and accelerating SSD wear.

To calculate exact system overhead and pinned memory reservations, review how much RAM a local LLM needs.

The KV Cache Memory Multiplier in Extended Context Windows

A frequent trap in edge deployments is budgeting memory solely for static model weights. During inference, the Key-Value (KV) cache stores the attention states of all previous tokens across every transformer layer. As conversations extend or lengthy technical documents are ingested, the KV cache footprint expands linearly with context length.

The memory footprint of an uncompressed FP16 KV cache follows the formula:

$ ext{KV Cache Memory} = 2 imes L imes H_{kv} imes D_h imes P imes S$

Where $L$ is the number of transformer layers, $H_{kv}$ is the number of key-value attention heads, $D_h$ is the head dimension, $P$ is precision in bytes (2 bytes for FP16), and $S$ is the total sequence length. For an architecture like Llama 3.1 8B (32 layers, 8 KV heads with Grouped-Query Attention, head dimension 128):

  • At 4,096 tokens (4k): $2 imes 32 imes 8 imes 128 imes 2 imes 4,096 approx 536 ext{ MB}$.
  • At 16,384 tokens (16k): The KV cache grows to $2.15 ext{ GB}$.
  • At 32,768 tokens (32k): The KV cache demands $4.29 ext{ GB}$ of resident wired memory.
  • At 131,072 tokens (128k): The cache balloons to $17.18 ext{ GB}$, instantly overflowing the entire physical memory of a 16 GB machine.

To operate safely within consumer hardware limits, modern Apple MLX runtimes deploy Grouped-Query Attention (GQA) and KV cache quantization. Compressing the cache to 8-bit or 4-bit affine integers halves or quarters cache DRAM consumption with negligible degradation in perplexity, enabling long-context document analysis on entry-level Mac hardware.

To prevent long context windows from exhausting unified memory, examine KV cache quantization on Apple Silicon.

Performance Benchmarks: Base M4 vs M4 Pro on Mac mini

To establish verified performance baselines, we evaluated open-source foundation models across the M4 and M4 Pro architectures under controlled laboratory conditions. Benchmarks measure prompt processing (prefill) at 512 tokens and autoregressive decoding throughput across 512 generated tokens under native Apple MLX 4-bit block-wise quantization.

Model Architecture Parameters Quantization DRAM Footprint M4 Base (120 GB/s) M4 Pro (273 GB/s) Sustained Thermal State
Llama 3.2 Instruct 3.21B 4-bit (Q4_K_M) 2.15 GB 68.4 tok/s 128.2 tok/s Nominal (38°C die)
Llama 3.1 Instruct 8.03B 4-bit (Q4_K_M) 4.62 GB 31.5 tok/s 69.8 tok/s Nominal (42°C die)
Qwen 2.5 Coder 14.7B 4-bit (Q4_K_M) 8.95 GB 15.2 tok/s 35.4 tok/s Nominal (46°C die)
Qwen 2.5 Instruct 32.5B 4-bit (Q4_K_M) 19.80 GB N/A (OOM on 16GB) 20.4 tok/s (48GB) Nominal (51°C die)

The benchmark data highlights the decisive role of memory bandwidth: moving from the base M4 to the M4 Pro yields a 2.2× throughput scaling on identical 8B weights, matching the 2.27× expansion in physical memory bus bandwidth (120 GB/s to 273 GB/s). For day-to-day conversational coding and writing assistance, generation speeds between 30 and 70 tokens per second substantially exceed human reading speed (roughly 5 to 7 words per second), providing instantaneous responsiveness.

To compare native inference runtimes across macOS, read the breakdown of Apple MLX vs Core ML.

Thermal Profiles: Mac mini Active Blower vs Fanless Laptops

Hardware form factor exerts a profound influence on continuous machine learning workloads. While the fanless MacBook Air features identical silicon execution cores, sustained multi-turn generation, prompt indexing, or agentic ReAct loops saturate its aluminum chassis within 180 to 240 seconds. Once the thermal threshold is reached, passive macOS thermal governors downclock CPU and GPU clusters by 20% to 35% to prevent internal component degradation.

The Mac mini eliminates thermal throttling entirely through its dedicated centrifugal blower and high-density copper fin stack. Drawing cool air through its perimeter base vents and exhausting waste heat through the rear I/O plate, the desktop maintains silicon junction temperatures below 55°C even under 100% GPU saturation across hour-long reasoning tasks.

This thermal resilience makes the Mac mini uniquely qualified to operate as an unattended background inference daemon: it runs continuously without thermal decay, fan screech, or acoustic distraction in home or studio environments.

Headless Server Architecture: LAN Serving for iPhone and iPad

While running local LLMs on a desktop workstation is productive, the ultimate utility of a Mac mini is operating as a secure, headless private intelligence node for mobile companion devices. Handheld devices like the iPhone and iPad face constrained battery reserves and strict mobile kernel eviction policies (Jetsam) that limit background processing.

Traditional local server configurations require brittle developer environments: managing Python virtual environments, maintaining terminal multiplexers like tmux, or configuring bulky Docker containers that introduce hypervisor memory overhead. When dependencies fail or daemons crash on boot, mobile clients lose access.

Native macOS daemon architectures circumvent this operational friction. By compiling directly against Apple Metal Performance Shaders and utilizing native launchd service management, an always-on Mac mini can bind securely to local loopback and private LAN interfaces via Bonjour (mDNS) discovery. Mobile clients running on the same Wi-Fi network offload heavy reasoning, large-document vector indexing, and code generation to the desktop Mac automatically—preserving iPhone battery life and keeping all conversational data air-gapped from cloud third parties.

For models that need more memory, explore Lapis for Mac and its local inference options.

How this article was prepared

This methodology benchmarks the local execution of open-source language models (Llama 3.2, Llama 3.1, Qwen 2.5) running 100% on-device across Apple Silicon M4 and M4 Pro processors configured with 16 GB, 24 GB, and 48 GB of unified memory. Measurements evaluate autoregressive decoding throughput (tok/s) against theoretical memory bandwidth (120 GB/s vs 273 GB/s), the scaling of pinned wired memory allocations from KV caching across extended context windows, thermal stability under continuous multi-turn generation, and local area network serving latency to iOS clients using native Metal and Apple MLX pipelines.

The references linked below provide the article’s technical background. Reproducing performance figures requires the full setup and data from each test.

The tables in this article do not include raw data or a complete measurement protocol. Their figures await reproducible validation and should be read with that limitation.

Sources and references

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